• CPU Configuration

• 1Kx13 bits on-chip ROM
• 32x8 bits on-chip registers (SRAM, general purpose)
• 5 level stacks for subroutine nesting
• Less than 1.5 Ma at 5V/4MHz
• Typically 15 Ua, at 3V/32kHz
• Typically 1 Ua, during Sleep mode

• I/O Port Configuration

• 2 bidirectional I/O ports : P5, P6
• 1 Input and 11 I/O pins
• Wake-up port : P6
• 6 Programmable pull-down I/O pins
• 7 programmable pull-high I/O pins
• 7 programmable open-drain I/O pins
• External interrupt : P60

• Operating Voltage Range:

• OTP version:

Operating voltage range: 2.3V~5.5V

• Operating Temperature range: 0~70°C
• Operating Frequency range (base on 2 clocks):

• Crystal Mode:

DC~20MHz/2clks @ 5V; DC~100ns inst. Cycle @ 5V

DC~8MHz/2clks @ 3V; DC~250ns inst. Cycle @ 3V

DC~4MHz/2clks @ 2.3V; DC~500ns inst. Cycle @ 2.3V

• ERC Mode:

DC~4MHz/2clks @ 5V; DC~500ns inst. Cycle @ 5V

DC~4MHz/2clks @ 3V; DC~500ns inst. Cycle @ 3V

DC~4MHz/2clks @ 2.3V; DC~500ns inst. Cycle @ 2.3V

• IRC Mode: 

Oscillation mode : 4MHz, 8MHz, 1MHz, 455kHz

Process deviation : Typ ± 5.5%, Max ± 6%

Temperature deviation : ±10% (0°C~70°C )

• Peripheral Configuration

• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt

• Three available Interrupts:

• TCC overflow interrupt
• Input-port status changed interrupt (wake-up from sleep mode)
• External interrupt

• Special Features

• Programmable free running watchdog timer
• Power saving Sleep mode
• Selectable Oscillation mode

• Other Features

• Programmable prescaler of oscillator set-up time
• One security register to prevent intrusion of user's OTP memory code·
• One configuration register to match user's requirement
• Two clocks per instruction cycle
• Package Type:
• 14-pin DIP 300mil : EM78P153AD14J
• 14-pin SOP 150mil : EM78P153ASO14J